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APA2036
Stereo 2.6W Audio Power Amplifier
Features
General Description
The APA2036 is a stereo audio power amplifier in a TQFN4x4-16 package. To simplify the audio system design in notebook computer applications, the APA2036 combines a stereo bridge-tied mode for speaker drive and a stereo single-end mode for headphone drive into a single chip, where both modes are easily switched by the SE/BTL input control pin signal. When the APA2036 is in the BTL mode with 5V supply voltage, it is capable of delivering 2.4W/2.0W/1.3W of continuous output power per channel into 3/4/8 load (Speaker) with less than 1% THD+N respectively. When the APA2036 operates in the single-ended mode, it is capable of delivering 160mW/ 85mW of continuous output power per channel into 16/ 32 load (Headphone). The APA2036 also serves low-voltage applications well. The APA2036, with 3.3V supply voltage, provides 900mW (at 1% THD+N) per channel into 4 load. Both of the depop circuitry and the thermal shutdown protection circuitry are integrated in the APA2036. The depop function reduces pops and clicks noise during power on/off and enable/shutdown processes. The thermal protection protects the chip from being destroyed by over-temperature failure. For power sensitive applications, the APA2036 also features a shutdown function which reduces the supply current only 0.5A (typical). THD+N vs. Output Power
10
* * * *
Operating Voltage: 3.0 ~ 5.5V Low Shutdown Current - IDD= 0.5A (typical) at VDD= 5V Selectable Bridge-Tied Load (BTL) or SingledEnded (SE) Operation Output Power (BTL) at 1% THD+N, VDD= 5V - 2.4W at RL = 3 - 2.0W at RL = 4 - 1.3W at RL = 8 Output Power (SE) at 1% THD+N, VDD= 5V - 160mW at RL = 16 - 85mW at RL = 32 Depop Circuitry Integrated Thermal and Over-Current Protections Short Circuit Protection Space Saving Packaging - 4mmx4mm 16-Lead Thin QFN Package (TQFN4X4-16) Lead Free Available (RoHS Compliant)
* * * * * * * * *
Applications
Handsets Portable multimedia devices Notebooks
Simplified Application Circuit
LOUTP
VDD=5V RL=4 Ci=1F BW<80KHz BTL mode
1
THD+N (%)
L-CH Input
LINN LBYPASS
Fin=20KHz
LOUTN
SE-BTL Signal
APA2036 R-CH Input
RINN RBYPASS ROUTN ROUTP
0.1
Fin=20Hz
Fin=1KHz
0.01 10m
100m
1
2
4
Output Power (W)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 1 www.anpec.com.tw
APA2036
Ordering and Marking Information
APA2036
Lead Free Code Handling Code Temperature Range Package Code Package Code QB : TQFN4x4-16 Operating Ambient Temperature Range I : - 40 to 85 C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device XXXXX - Date Code
APA2036 QB :
APA2036 XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the leadfree requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
Pin Configuration
12 RBYPASS 10 LBYPASS 11 GND 9 GND
RINN 13 ROUTP 14 VDD 15 ROUTN 16 APA2036 TOP VIEW TQFN4x4-16
8 LINN 7 LOUTP 6 VDD 5 LOUTN
=Thermal Pad (connected the Thermal Pad to GND plane for better heat dissipation)
GND 1
SE/BTL 2
SHUTDOWN 3
Absolute Maximum Ratings
Symbol VDD Supply Voltage
GND 4
(Note 1)
Rating -0.3 to 6 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -40 to 85 150 -65 to +150 260 Internally Limited Unit V V V

Parameter
Input Voltage (SE/BTL, SHUTDOWN, RINN, LINN, RBYPASS, LBYPASS) Output Voltage (ROUTP, ROUTN, LOUTP, LOUTN) TA TJ TSTG TSDR PD Operating Ambient Temperature Range Maximum Junction Temperature Storage Temperature Range Maximum Lead Soldering Temperature, 10 seconds Power Dissipation
C C C
C
W
Note 1G Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 2 www.anpec.com.tw
APA2036
Thermal Characteristics (Note 2,3)
Symbol Parameter Thermal Resistance - Junction to Ambient Junction-to-Case Resistance in free air
(Note 2)
Value 41 9
Unit
o
JA
JC
(Note 3)
C/W
Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The thermal pad of TQFN4x4-16 is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the thermal pad on the underside of the TQFN4x4-16 package.
Recommended Operating Conditions
Symbol VDD VIH VIL VIC TA TJ RL RL Supply Voltage High level threshold voltage SHUTDOWN SE/BTL Low level threshold voltage Common mode input voltage Ambient Temperature Range Junction Temperature Range Speaker Resistance Headphone Resistance SHUTDOWN SE/BTL Parameter Range 3.0 ~ 5.5 0.4 VDD ~ VDD 0.8 VDD ~ VDD 0 ~ 1.0 0 ~ 0.6VDD ~ VDD-0.5 -40 ~ 85 -40 ~ 125 3~ 16 ~ Unit V V V V V V
o
C C
o

Electrical Characteristics
Unless otherwise noted, these specifications apply over VDD=5V, VGND=0V, TA= -40 ~ 85OC, Typical values are at TA= 25OC
Symbol VDD IDD ISD TSTART-UP Parameter Supply Voltage VSE/BTL=0V Supply Current Shutdown Current Start-Up time from shutdown VSE/BTL=5V VSHUTDOWN=5V CB=2.2F Test Condition APA2036 Min. 3 5.5 3 0.5 700 Typ. Max. 5.5 13.5 mA 7.5 5 A ms Unit V
BTL mode, VDD=5V RL=3 THD+N=1%, Fin=1KHz PO Output Power THD+N=10%, Fin=1KHz RL=4 RL=8 RL=3 RL=4 RL=8 Total Harmonic Distortion Pulse Noise RL=4 PO=1.3W RL=8 PO=0.9W 1.1 2.4 2.0 1.3 W 3.0 2.6 1.6 0.06 % 0.03
THD+N
Fin=1KHz
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APA2036
Electrical Characteristics (Cont.)
Unless otherwise noted, these specifications apply over VDD=5V, VGND=0V, TA= -40 ~ 85OC, Typical values are at TA=25OC
Symbol PSRR VOS Crosstalk S/N Vn Parameter Power Supply Rejection Ratio Output Offset Voltage Channel separation Signal to Noise Ratio Noise Output Voltage Test Condition RL=8, Fin=217Hz VIN=0V RL=8, PO=0.9W, Fin=1KHz RL=8, PO=1.1W, A_weighting RL=8 APA2036 Min. Typ. 61 10 100 93 22 Max. Unit dB mV dB dB V(rms)
SE mode, VDD=5V RL=16 THD+N=1%, Fin=1KHz RL=32 PO Output Power THD+N=10%, Fin=1KHz THD+N PSRR VOS Crosstalk S/N Vn Total Harmonic Distortion Pulse Noise Power Supply Rejection Ratio Output Offset Voltage Channel separation Signal to Noise Ratio Noise Output Voltage Fin=1KHz RL=32, Fin=217Hz VIN=0V RL=32, PO=60mW, Fin=1KHz RL=32, PO=65mW, A_weighting RL=32 RL=16 RL=32 RL=32 PO=60mW 210 110 0.02 60 10 85 100 8 % dB mV dB dB V(rms) 70 85 mW 160
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APA2036
Typical Operating Characteristics
THD+N vs. Output Power
10
THD+N vs. Output Power
10
VDD=5V RL=4 Ci=1F BW<80KHz BTL mode
1
1
VDD=5V RL=8 Ci=1F BW<80KHz BTL mode
Fin=20KHz
THD+N (%)
Fin=20KHz
THD+N (%)
0.1
Fin=20Hz
0.1
Fin=20Hz
Fin=1KHz
0.01 10m
Fin=1KHz
0.01 10m
100m
1
2
4
100m
1
2
3
Output Power (W)
Output Power (W)
THD+N vs. Output Power
10
THD+N vs. Output Power
10
THD+N (%)
THD+N (%)
1
VDD=5V RL=16 Ci=1F Cc=1000F BW<80KHz SE mode
Fin=20Hz
1
VDD=5V RL=32 Ci=1F CC=1000F BW<80KHz SE mode
Fin=20Hz
Fin=20KHz
0.1
0.1
Fin=20KHz
Fin=1KHz
0.01 10m
Fin=1KHz
0.01 10m
100m
300m
100m
200m
Output Power (W)
Output Power (W)
THD+N vs. Output Power
10
THD+N vs. Output Power
10
VDD=3.3V RL=4 Ci=1F BW<80KHz BTL mode
VDD=3.3V RL=8 Ci=1F BW<80KHz BTL mode
1
1
THD+N (%)
THD+N (%)
Fin=20KHz
Fin=20KHz
0.1
Fin=20Hz
0.1
Fin=20Hz
Fin=1KHz
Fin=1KHz
0.01 10m
0.01 10m
100m
1
2
100m
1
Output Power (W)
Output Power (W)
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APA2036
Typical Operating Characteristics (Cont.)
THD+N vs. Output Power
10
THD+N vs. Output Power
10
1
VDD=3.3V RL=16 Ci=1F CC=1000F BW<80KHz SE mode
THD+N (%)
Fin=20KHz
0.1
THD+N (%)
Fin=20Hz
1
VDD=3.3V RL=32 Ci=1F CC=1000F BW<80KHz SE mode
0.1
Fin=20KHz
Fin=1KHz
Fin=20Hz Fin=1KHz
0.01 10m
20m
50m
100m
0.01 10m
20m
50m
100m
Output Power (W)
Output Power (W)
THD+N vs. Frequency
10
THD+N vs. Frequency
10
THD+N (%)
THD+N (%)
VDD=5V RL=4 Ci=1F PO=1.3W 1 BW<80KHz BTL mode
1
VDD=5V RL=8 Ci=1F PO=0.9W BW<80KHz BTL mode
0.1
Left Channel Right Channel
0.1
Right Channel
0.01
0.01
Left Channel
0.001 20
100
1K
10K 20K
0.001 20
100
1K
10K 20K
Frequency (Hz)
Frequency (Hz)
THD+N vs. Frequency
10
10
THD+N vs. Frequency
VDD=5V RL=32 Ci=1F CC=1000F PO=60mW BW<80KHz SE mode
1
THD+N (%)
THD+N (%)
VDD=5V RL=16 Ci=1F CC=1000F PO=110mW BW<80KHz SE mode
1
0.1
0.1
Right Channel
0.01
Right Channel
Left Channel
0.01
Left Channel
0.001 20
100
1K
10K 20K
0.001 20
100
1K
10K 20K
Frequency (Hz)
Frequency (Hz)
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APA2036
Typical Operating Characteristics (Cont.)
Crosstalk vs. Frequency
+0 -10 -20 -30 -40
Crosstalk vs. Frequency
+0 -10 -20 -30
Crosstalk (dB)
-50 -60 -70 -80 -90 -100 -110 -120 20 100
Left to Right Right to Left
Crosstalk (dB)
VDD=5V RL=4 Ci=1F PO=1.3W BW<80KHz BTL mode
-40 -50 -60 -70 -80 -90 -100 -110
VDD=5V RL=8 Ci=1F PO=0.9W BW<80KHz BTL mode
T
Left to Right
Right to Left
1K
10K 20K
-120 20
100
1K
2K
20K
Frequency (Hz)
Frequency (Hz)
Crosstalk vs. Frequency
+0 -10 -20 -30 -40
Crosstalk vs. Frequency
+0 -10 -20 -30 -40
Crosstalk (dB)
-50 -60 -70 -80 -90 -100 -110 -120 20
Crosstalk (dB)
VDD=5V RL=16 Ci=1F Cc=1000uF PO=110mW BW<80KHz SE mode
-50 -60 -70 -80 -90 -100 -110
VDD=5V RL=32 Ci=1F Cc=1000uF Po=60mW BW<80KHz SE mode
Left to Right
Left to Right Right to Left
Right to Left
100
1K
10K 20K
-120 20
100
1K
10K 20K
Frequency (Hz)
Frequency (Hz)
Output Noise Voltage vs. Frequency
50
Output Noise Voltage vs. Frequency
50
Output Noise Voltage (Vrms)
Output Noise Voltage (Vrms)
Right Channel
20
Right Channel
20
Left Channel
10
Left Channel
10
VDD=5V RL=4 Ci=1F BW<80KHz A-Weighting BTL mode
1 20 100 1K 2K 10K 20K
VDD=5V RL=8 Ci=1F BW<80KHz A-Weighting BTL mode
1 20 100 1K 10K 20K
Frequency (Hz)
Frequency (Hz)
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APA2036
Typical Operating Characteristics (Cont.)
Output Noise Voltage vs. Frequency
50 50
Output Noise Voltage vs. Frequency
Output Noise Voltage (Vrms)
Output Noise Voltage (Vrms)
20
20
10
Right Channel Left Channel
10
Right Channel Left Channel
VDD=5V RL=16 Ci=1F BW<80KHz A-Weighting SE mode
1 20 50 100 200 500 1K 2K 5K 10K 20K
VDD=5V RL=32 Ci=1F BW<80KHz A-Weighting SE mode
1 20 50 100 200 500 1K 2K 5K 10K 20K
Frequency (Hz)
Frequency (Hz)
Frequency Response
+8 +120
Frequency Response
+8 +120
Gain
+6 +60
Gain
+6 +60
Phase(deg)
Phase
+4 +0
Phase
+4 +0
+2
VDD=5V RL=4 Ci=1F PO=130mW BTL mode
10 100 1K 10K
-60
+2
VDD=5V RL=8 Ci=1F PO=90mW BTL mode
10 100 1K 10K
-60
+0
-120 100K 200K
+0
-120 100K 200K
Frequency (Hz)
Frequency (Hz)
Frequency Response
-0 +270
Frequency Response
-0 +270
Gain
-1 +240
Gain
-1 +240
-2
+210
-2
+210
Phase(deg)
Phase
-3 +180
Phase
-3 +180
-4
-5
VDD=5V RL=16 Ci=1F CC=1000F PO=11mW SE mode
100 1K 10K
+150
-4
+120
-5
VDD=5V RL=32 Ci=1F CC=1000F PO=6mW SE mode
10 100 1K 10K
+150
+120
-6 10
+90 100K 200K
-6
+90 100K 200K
Frequency (Hz)
Frequency (Hz)
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Phase(deg)
Gain(dB)
Gain(dB)
Phase(deg)
Gain(dB)
Gain(dB)
APA2036
Typical Operating Characteristics (Cont.)
PSRR vs. Frequency
+0 -10 -20 -30 -40 -50 -60
PSRR vs. Frequency
+0 -10 -20
VDD=5V RL=4 CB=2.2F Vrr=200mVrms BTL mode
VDD=5V RL=8 CB=2.2F Vrr=200mVrms BTL mode
PSRR (dB)
PSRR (dB)
-30 -40 -50
Left Channel
Left Channel
-60
Right Channel
-70 -80 20
-70 -80 20
Right Channel
100
1K
10K 20K
100
1K
10K
20K
Frequency (Hz)
Frequency (Hz)
PSRR vs. Frequency
+0 -10 -20
+0
PSRR vs. Frequency
-10 -20 -30 -40 -50 -60
VDD=5V RL=16 CB=2.2F Vrr=200mVrms SE mode
VDD=5V RL=32 CB=2.2F Vrr=200mVrms SE mode
PSRR (dB)
-40 -50
Right Channel
-60 -70 -80 20
PSRR (dB)
-30
Left Channel Right Channel
Left Channel
-70 -80 20
100
1K
10K 20K
100
1K
10K 20K
Frequency (Hz)
Frequency (Hz)
Output Power vs. Supply Voltage
4.0 3.5 3.0
2.00
Output Power vs. Supply Voltage
RL=8 Ci=1F Fin=1KHz BTL mode
RL=4 Ci=1F Fin=1KHz BTL mode
1.75 1.50
Output Power (W)
2.5 2.0 1.5 THD+N=1% 1.0 0.5 0.0 THD+N=10%
Output Power (W)
1.25 1.00 0.75 0.50 0.25 0.00
THD+N=10%
THD+N=1%
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage (Volt)
Supply Voltage (Volt)
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APA2036
Typical Operating Characteristics (Cont.)
Output Power vs. Supply Voltage
300
Output Power vs. Supply Voltage
150
250
Output Power (mW)
200 THD+N=10%
Output Power (mW)
RL=16 Ci=1F CC=1000F Fin=1KHz SE mode
125
100
RL=32 Ci=1F CC=1000F Fin=1KHz SE mode
THD+N=10%
150
75 THD+N=1% 50
100
THD+N=1%
50 0 3.0
25
3.5
4.0
4.5
5.0
5.5
0 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (Volt)
Supply Voltage (Volt)
Power Dissipation vs. Output Power
1.4 1.2
Power Dissipation vs. Output Power
100 RL=16 80
RL=4
1.0 0.8 0.6 0.4 RL=8
Power Dissipation(mW)
Power Dissipation(W)
60
RL=32
40
0.2 0.0
VDD=5V THD+N<1% BTL mode
0.0 0.5 1.0 1.5 2.0 2.5
20
VDD=5V THD+N<1% SE mode
0 50 100 150 200
0
Output Power (W)
Output Power (mW)
Supply Current vs. Output Power
0.8
50
Supply Current vs. Output Power
40
0.6 RL=4 0.4
Supply Current (mA)
RL=16 30
Supply Current (A)
20
RL=32
RL=8 0.2
VDD=5V THD+N<1% BTL mode
0.0 0.0 0.5 1.0 1.5 2.0 2.5
10
VDD=5V THD+N<1% SE mode
0 50 100 150 200
0
Output Power (W)
Output Power (mW)
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APA2036
Typical Operating Characteristics (Cont.)
Supply Current vs. Supply Voltage
6.0
GSM Power Supply Rejection vs. Frequency
Supply Voltage (dBV)
+0
No Load
5.0 BTL mode
-50
Supply Current (mA)
4.0
-100
3.0
Output Voltage (dBV)
SE mode
+0
-150
2.0
-50
1.0
-100
0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-150
0
400
800
1.2K
1.6K
2K
Supply Voltage (Volt)
Frequency (Hz)
GSM Power Supply Rejection vs. Time
VDD 1
Output Transient at Power-On
VDD
VOUT 3
VOUT 2
1,2
VOUTP
CH1: VDD, 500mV/Div, DC Voltage Offset = 5.0V CH2: VOUT (VOUTP-VOUTN), 20mV/Div, DC TIME: 20ms/Div
CH1: VDD, 1V/Div, DC CH2: VOUTP, 1V/Div, DC CH3: VOUT (VOUTP-VOUTN), 50mV/Div, DC TIME: 100ms/Div
Output Transient at Shutdown Active
Output Transient at Shutdown Release
VSHUTDOWN
3
VOUT
VOUT 3 VOUTP
VOUTP VSHUTDOWN 1,2 1,2
CH1: VSHUTDOWN, 1V/Div, DC CH2: VOUTP, 1V/Div, DC CH3: VOUT(VOUTP-VOUTN), 50mV/Div, DC TIME: 500ms/Div
CH1: VSHUTDOWN, 1V/Div, DC CH2: VOUTP, 1V/Div, DC CH3: VOUT(VOUTP-VOUTN), 50mV/Div, DC TIME: 100ms/Div
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APA2036
Block Diagram
LINN LOUTP
LBYPASS
Bias Voltage Generator
LOUTN RINN ROUTP
RBYPASS
Bias Voltage Generator
ROUTN SE/BTL
SE/BTL Mode Selection Power and Depop circuit
VDD GND
SHUTDOWN
Shutdown circuit
Pin Description
Pin NO. 1,4,9,11 2 3 5 6,15 7 8 10 12 13 14 16 Name GND SE/BTL SHUTDOWN LOUTN VDD LOUTP LINN LBYPASS RBYPASS RINN ROUTP ROUTN Function Description Ground connection of circuitry. Connect all GND pins to the thermal pad and system ground plane. Output Mode control pin, high for SE output mode and low for BTL mode. Shutdown mode control pin. Pulling high the voltage on this pin shuts off the IC. In shutdown mode, the IC only draws 0.5A (typical) of supply current. Left channel output in BTL mode, high impedance in SE mode. Supply voltage input pin. Connect all of the VDD pins to supply voltage. Left channel output in BTL mode and SE mode. As "Typical Application Circuit" shown, this pin' output signal is inverted against LINN input signal. s Left channel input terminal. Bypass capacitor connection pin for the bias voltage generator. Bypass capacitor connection pin for the bias voltage generator. Right channel input terminal. Right channel output in BTL mode and SE mode. As "Typical Application Circuit" shown, this pin' output signal is inverted against RINN input signal. s Right channel output in BTL mode, high impedance in SE mode.
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APA2036
Typical Application Circuit
VDD Cs 0.1F RfL 20K LINN LOUTP 100F LBYPASS CB 2.2F Bias Voltage Generator 4 LOUTN 10F
CiL 1F L-CH Input
RiL 20K
VDD
GND CCL
1K
SE/BTL Signal
Control Pin Ring
CinR RiR 1F 20K R-CH Input RfR 20K
RINN ROUTP
CCR
Sleeve Tip Headphone Jack
RBYPASS VDD
Bias Voltage Generator
100F 1K 4 ROUTN
100K
SE/BTL Signal Shutdown Signal
100K
SE/BTL SHUTDOWN
SE/BTL Mode Selection Shutdown circuit
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APA2036
Function Description
Bridge-Tied Load (BTL) Operation
Rf Ri OUTP OP1
Single-Ended (SE) Operation To consider the single-supply SE configuration shown in Typical Application Circuit, a coupling capacitor is required to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33F to 1000F) so they tend to be expensive, occupy valuable
RL OUTN
PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor). SE/BTL Mode Selection Function Eazy switch between BTL and SE modes is one of its most important costs saving features for the APA2036. This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated. Inside of the APA2036, two separate amplifiers drive OUTP and OUTN (see Figure 1). The SE/BTL input controls the operation of the follower amplifier that drives LOUTP and ROUTN.
OP2 Bias Voltage Generator
Figure 1: APA2036 internal configuration (each channel) The power amplifier' (OP1) gain is set by external resiss tance Ri and Rf, while the second amplifier (OP2) is internally fixed in a unity-gain and inverting configuration. Figure 1 shows that the output of OP1 is connected to the input of OP2, which results in the output signals of both amplifiers with identical in magnitude, but out of phase 180. Consequently, the differential gain for each channel is 2X (Gain of SE mode). By driving the load differentially through outputs OUTP and OUTN, an amplifier configuration is commonly referred to established bridged mode. BTL mode operation is different from the classical single-ended SE amplifier configuration where one side of its load is connected to ground. A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus doubles the output swing for a specified supply voltage. Four times the output power is possible as compared with a SE amplifier in the same conditions. A BTL configuration, such as the one used in the APA2036, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUTP, ROUTN, LOUTP, and LOUTN, are biased at half-supply, DC voltage doesn' t have to exist across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration.
* *
When SE/BTL keeps low, the OP2 turns on and the APA2036 is in the BTL mode. When SE/BTL keeps high, the OP2 is in a high output impedance state, which configures the APA2036 as SE driver from OUTP. IDD is reduced by approximately one-half in SE mode.
Control of the SE/BTL input can be a logic-level TTL source or a resistor divider network or the stereo headphone jack with switch pin as shown in Typical Application Circuit.
1K VDD 100K SE/BTL
Tip Sleeve Control Pin
Ring
Headphone Jack
Figure 2: SE/BTL input selection by phonejack plug
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APA2036
Function Description (Cont.)
SE/BTL Mode Selection Function (Cont.) In Figure 2, input SE/BTL operates as below: When the phonejack plug is inserted, the 1K resistor is disconnected and the SE/BTL input is pulled high to enable the SE mode. Meanwhile, the OUTN amplifier is shut down which turns the speaker to be mute. The OUTP amplifier then drives through the output capacitor into the headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, and the voltage divider is set up by resistors 100K and 1K. Resistor 1K then is pulled low the SE/BTL pin, enabling the BTL function. Shutdown Function In order to reduce power consumption while not in use, the APA2036 with shutdown function externally turns off the amplifier bias circuitry. This shutdown feature turns the amplifier off when logic high is placed on the SHUTDOWN pin for the APA2036. The trigger point between a logic high and logic low level is typical 0.4VDD. It would be better to switch between ground and the supply voltage VDD to provide maximum device performance. By switching the SHUTDOWN pin to high level, the amplifier enters a low consumption current state; IDD for the APA2036 is in shutdown mode. In normal operation, the APA2036' s SHUTDOWN pin should be pulled to low level to keep the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite voltage to avoid unwanted state changes. Thermal Protection The over-temperature circuit limits the junction temperature of the APA2036. When the junction temperature exceeds T J = +150 oC, a thermal sensor turns off the amplifier, allowing the devices to cool. The thermal sensor allows the amplifier to start up after the junction temperature cools down about 125oC. The thermal protection designed with a 25oC hysteresis lowers the average TJ during continuous thermal overload conditions, which is increasing lifetime of the IC. Over-Current Protection The APA2036 monitors the output current. When the current exceeds the current-limit threshold, the APA2036 turns off the output to prevent the IC damages from over-current or short-circuits condition. When the over-current occurs in power amplifier, the output buffer' current will s be foldbacked to a low setting level, and it will release when over-current situation is no long existence. On the contrary, if the over-current period is long enough and the IC' junction temperature reaches the thermal protection s threshold, the IC will enter thermal protection mode.
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APA2036
Application Information
Input Resistance (Ri) The gain of the APA2036 is set by the external resistors (Ri and Rf). R BTL Gain = -2 x f Ri SE Gain = - Rf Ri (1) Effective Bypass Capacitor (CB) As other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitors located on the bypass and power supply pins should be as close to the device as possible. The effect of a larger half-supply bypass capacitor will improve PSRR due to increased half-supply stability. Typi(2) cal application employs a 5V regulator with 1.0F and a 0.1F bypass as supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2036. The selection of bypass capacitors, especially CB, thus depends upon desired PSRR requirements, click-and-pop performance. To avoid start-up pop noise occurred, the bypass voltage should rise slower than the input bias voltage and the relationship shown in equation (5) should be maintained. V (5) CB B + 0.4 > 3RiCi 20 The bypass capacitor is fed from a 160K resistor inside the amplifier. Bypass capacitor, CB, values of 1F to 2.2F ceramic or tantalum low-ESR capacitors are recommended for the best THD+N and noise performance. The bypass capacitance also effects the start up time. It is determined in the following equation: V Tstart-up = CB B + 0.4 (6) 20 1 Note : VB = VDD 2 For example, if CB=2.2F, VDD=5V, then the start-up time is 0.68s. Output Coupling Capcaitor (CC) In the typical single-supply SE configuration, an output coupling capacitor (CC) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a highpass filter governed by following equation: 1 FC(highpass ) = (7) 2RLCC For example, a 330F capacitor with an 8 speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is typically small load impedance, which drives the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load.
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BTL mode operation brings the factor of 2 in the gain equation due to the inverting amplifier mirroring the voltage swing across the load. The input resistance will affect the low frequency performance of audio signal. Input Capacitor (Ci) In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri from a high-pass filter with the corner frequency are determined in the following equation: FC(highpass ) = 1 2R iCi (3)
The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 20K and the specification calls for a flat bass response down to 40Hz. Equation is reconfigured as followed: Ci = 1 2R iFC (4)
Consider to input resistance variation, the Ci is 0.2F, so one would likely choose a value in the range of 0.22F to 1.0F. A further consideration for this capacitor is the leakage path from the input source through the input network (Ri +Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a lowleakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level is held at VDD/2, which is likely higher than the source DC level. Please note that it is important to confirm the capacitor polarity in the application.
APA2036
Application Information (Cont.)
Power Supply Decoupling (CS) The APA2036 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different capacitors that target on different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalentseries-resistance (ESR) ceramic capacitor, typically 0.1F is placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10F or greater placed near the audio power amplifier is recommended. Optimizing Depop Circuitry Circuitry has been included in the APA2036 to minimize the amount of popping noise at power-up while not in shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate click-andpop, all capacitors must be fully discharged before turnon. Rapid on/off switching of the device or the shutdown function will cause the click-and-pop circuitry. The value of Ci will also affect turn-on pops (refer to Effective Bypass Capacitance). The bypass voltage rises up but should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of CB can be changed to alter the device turn-on time and the amount of click-and-pops. By increasing the value of CB, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the size of CB and the turn-on time. In a SE configuration, the output coupling capacitor (CC) is the particular concern. This capacitor discharges through the internal 10K resistors. Depending on the size of CC, the time constant can be relatively large. To reduce transients in SE mode, an external 1K resistor can be placed in parallel with the internal 10K resistor. The tradeoff for using this resistor is an increase in quiescent current.
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In the most cases, choosing a small value of Ci in the range of 0.22F to 1F and CB being equal to 2.2F should cause a virtually click-less and pop-less turn-on. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. Therefore it is advantageous to use low-gain configurations. BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power is delivered to the load. The following equations are the basis for calculating amplifier efficiency. P (8) Efficiency = O PSUP where: 2 2 V V (9) PO = O.RMS = P 2RL RL VO.RMS = VP 2 (10) (11)
2VP RL Efficiency of a BTL configuration: 2 VP PO 2RL VP = = 2VP 4VDD PSUP VDD x RL PSUP = VDD x IDD.AVG = VDD
(12)
Table 1 is for calculating efficiency for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in nearly flat internal power dissipation over the normal operating range. In addition, the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8 loads and a 5V supply, the maximum draw on the power supply is almost 3W. In the equation, VDD is in the denominator. One last key point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation (12), VDD is in the denominator. This indicates that as VDD goes down, and efficiency goes up. In other words, choosing the correct supply voltage and speaker impedance for the application by using the efficiency analysis.
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APA2036
Application Information (Cont.)
BTL Amplifier Efficiency (Cont.)
PO (W) 0.25 0.50 1.00 1.25 Efficiency (%) 30.37 43.37 61.65 69.03 IDD (A) 0.16 0.23 0.32 0.36 VPP (V) 2.00 2.83 4.00 4.47 PO (W) 0.57 0.65 0.62 0.56
Thermal Consideration Linear power amplifiers dissipates a significant amount of heat in the package in normal operating condition. The first consideration to calculate maximum ambient temperatures is the numbers from the Power Dissipation vs. Output Power graphs are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given JA, the maximum allowable junction temperature (TJMax), the total internal dissipation (PD), and the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2036 is 150C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. TAMax = TJMax -JA x PD 150 - 45 (0.8x2) = 78C (13) (16)
* *High peak voltages cause increasing of the THD+N. Table 1. Efficiency vs. Output Power in 5-V/8 Differential Amplifier Systems Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. Equation (13) states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load.
SE mode : PD, MAX = VDD
2
2 2R L
The APA2036 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150C to prevent damaging the IC. Layout Consideration
Thermal Via diameter 0.3mm x 4
In BTL mode operation, the output voltage swing is doubled in SE mode. Thus the maximum power dissipation point for a BTL mode operated at the same given conditions is 4 times in SE mode.
BTL mode : PD, MAX = 2 VDD
2
2R L
(14)
1mm 0.5mm 2.5mm
power dissipation from equation (14), assuming a 5V power supply and an 8 load, must not be greater than the power dissipation that results from the equation (15):
PD, MAX = TJ, MAX - TA JA
0.65mm 2.5mm
Ground plane for Thermal PAD
(15)
Since the maximum junction temperature (TJ.MAX) of the APA2036 is 150OC and the ambient temperature (TA) is defined by the power system design, the maximum power dissipation, which the IC package is able to handle, can be obtained from equation (15). Once the power dissipation is greater than the maximum limit (PD, Max), the supply voltage (VDD) must be decreased, the load impedance (R L) must be increased or the ambient temperature should be reduced.
Figure 3: TQFN4x4-16 Land Pattern Recommendation
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4.9mm
Even with this substantial increase in power dissipation, the APA2036 does not require extra heatsinking. The
APA2036
Application Information (Cont.)
Layout Consideration (Cont.) 1. All components should be placed close to the APA2036. For example, the input capacitor (Ci) should be close to APA2036' input pins to avoid causing noise cous pling to APA2036' high impedance inputs; the s decoupling capacitor (CS ) should be placed by the APA2036' power pin to decouple the power rail noise. s 2. The output traces should be short, wide (>50mil) and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should be greater than 50mil. 5. The TQFN4X4-16 Thermal PAD should be soldered on PCB, and the ground plane needs soldered mask (to avoid short circuit) except the Thermal PAD area.
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APA2036
Package Information
TQFN4x4-20
D
A E D2
E2
Pin 1 Corner
A1 A3
e S Y M B O L A A1 A3 b D D2 E E2 e L 0.30 2.50 0.65 BSC 0.50 0.012 2.50 4.00 BSC 2.80 0.098 0.026 BSC 0.020 0.25 4.00 BSC 2.80 0.098 0.157 BSC 0.110 TQFN4x4-16 MILLIMETERS MIN. 0.70 0.00 0.20 REF 0.35 0.010 0.157 BSC 0.110 MAX. 0.80 0.05 MIN. 0.028 0.000 0.008 REF 0.014 INCHES MAX. 0.031 0.002
Note : Follow JEDEC MO-220 WGGC-3.
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L
b
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APA2036
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
T1 C d D W E1 F 12.4+2.00 13.0+0.50 330.0O .00 50 MIN. 2 0 0 0 1.5 MIN. 20.2 MIN. 12.0O .30 1.75O .10 5.5O .10 -0.00 -0.20 TQFN 4x4-16 P0 P1 P2 D0 D1 T A0 B0 K0 1.5+0.10 0.6+0.00 4.0O .10 8.0O .10 2.0O .10 0 0 0 4.30O .20 4.30O .20 1.30O .20 0 0 0 1.5 MIN. -0.00 -0.40
Application
A
H
H A
T1
W
(mm)
Devices Per Unit
Package Type TQFN4x4-16 Unit Tape & Reel Quantity 3000
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APA2036
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone TL to TP Ramp-up
TL
Temperature
tL Tsmax
Tsmin Ramp-down ts Preheat
25
t 25C to Peak
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78
Time
Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Time 25C to Peak Temperature Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds 6C/second max. 6 minutes max. Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds 6C/second max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
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APA2036
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures Package Thickness <2.5 mm 2.5 mm Volume mm <350 240 +0/-5C 225 +0/-5C
3
Volume mm3 350 225 +0/-5C 225 +0/-5C
Table 2. Pb-free Process - Package Classification Reflow Temperatures Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level. Package Thickness
3 3 3
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
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